FVP: A formal verification platform for SoC

被引：0

作者：

Liao, WS ^{[1
]}

Hsiung, PA ^{[1
]}

机构：

[1] Natl Chung Cheng Univ, Dept Comp Sci & Informat Engn, Chiayi, Taiwan

来源：

IEEE INTERNATIONAL SOC CONFERENCE, PROCEEDINGS | 2003年

关键词：

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

How to verify a System-on-a-Chip (SoC) has been an important issue in an SoC design process due to its complexity. The capacity of traditional verification techniques such as simulation or emulation is no longer suitable for SoC. However, formal verification that provides 100% coverage and counterexamples is expected to be a complementary solution. Several researches on formally verifying an SoC have demonstrated its feasibility and benefits. Nevertheless, there is no utility for platform based formal verification of SoC as yet. A Formal Verification Platform (FVP) is proposed to formally verify an Intellectual Property (IP) by providing a formal platform to create its environment. We will illustrate our modeling experiences using the model checker SGM.

引用

页码：21 / 24

页数：4

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