A 9-bit Low-Power Fully Differential SAR ADC Using Adaptive Supply and Reference Voltages

被引：0

作者：

Navidi, Seyedeh Masoumeh ^{[1
]}

Ehsanian, Mehdi ^{[1
]}

机构：

[1] KN Toosi Univ Technol, Dept Elect Engn, Tehran, Iran

来源：

26TH IRANIAN CONFERENCE ON ELECTRICAL ENGINEERING (ICEE 2018) | 2018年

关键词：

ADC; analog-to-digital conversion; CMOS analog integrated circuits; low-power electronics; successive approximation register; CMOS;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents a 9-bit hilly differential 200KS/s low-power successive-approximation-register (SAR) analog-to-digital converter (ADC). Adaptive comparator supply voltage and DAC reference voltage are exploited to decrease the power consumption of these blocks in specific bit conversion steps. The proposed circuit was simulated using a 0.18 mu m standard CMOS process. The proposed SAR ADC achieves 51.9dB SNDR (8.3 ENOB) and 56.2dB SFDR with 200KS/sec. The total power consumption is 6.98 mu W from both 1.8V and 0.9V supplies.

引用

页码：205 / 210

页数：6

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