A 9-bit Low-Power Fully Differential SAR ADC Using Adaptive Supply and Reference Voltages

This paper presents a 9-bit hilly differential 200KS/s low-power successive-approximation-register (SAR) analog-to-digital converter (ADC). Adaptive comparator supply voltage and DAC reference voltage are exploited to decrease the power consumption of these blocks in specific bit conversion steps. The proposed circuit was simulated using a 0.18 mu m standard CMOS process. The proposed SAR ADC achieves 51.9dB SNDR (8.3 ENOB) and 56.2dB SFDR with 200KS/sec. The total power consumption is 6.98 mu W from both 1.8V and 0.9V supplies.