A new flip chip packaging technology for the mid-range application space

A new flip chip packaging technology is developed which entails fine pitch bumping and assembly of standard die with perimeter bonding pads. The technology provides compelling advantages for the packaging of IC's in the mid range application space (up to similar to 700 pins) represented by devices such as ASIC's, graphics processors, DSP's, RF/analog and others. The flip chip interconnection is accomplished by the use of gold stud bumps on the die, attached by thermo-compression bonding to low-cost substrates with pre-dispensed non-conductive adhesive (NCA) in lieu of conventional underfilling. In this paper, the structure, assembly process and reliability data of the package are presented. High levels of component level reliability are demonstrated, previously believed to be unfeasible with similar package structures. Extension of the inteconnect techhnology to finer pitch and higher pin counts (50 urn ptich / 1000 I/O) is discussed. Finally, the electrical design and routing methodology that simplifies the structure and layer count of the substrate over comparable area array solder bump substrate designs is presented.