NMOS and PMOS metal gate transistors with junctions activated by laser annealing

被引：0

作者：

Severi, S. ^{[1
,2
]}

Augendre, E. ^{[1
]}

Falepin, A. ^{[1
]}

Kerner, C. ^{[1
]}

Ramos, J. ^{[1
]}

Eyben, P. ^{[1
]}

Vandervost, W. ^{[1
]}

Curatola, C. ^{[3
]}

Felch, S. ^{[4
]}

Nouri, F. ^{[4
]}

Kraus, P. ^{[4
]}

Parihar, V. ^{[4
]}

Noda, T. ^{[5
]}

Schreutelkamp, R. ^{[4
]}

Hoffmann, T. Y. ^{[1
]}

Absil, P. ^{[1
]}

De Meyer, K. ^{[1
,2
]}

Jurczak, M. ^{[1
]}

Biesemans, S. ^{[1
]}

机构：

[1] Interuniv Microelect Ctr, IMEC, Kapeldreef 75, B-3001 Louvain, Belgium

[2] Katholieke Univ Leuven, ESAT INSYS, B-3001 Heverlee, Belgium

[3] Philips Res Leuven, B-3001 Heverlee, Belgium

[4] Appl Mat Inc, Sunnyvale, CA USA

[5] Matsushita Elect Ind Co Ltd, Kyoto 6018413, Japan

来源：

2006 INTERNATIONAL SYMPOSIUM ON VLSI TECHNOLOGY, SYSTEMS, AND APPLICATIONS (VLSI-TSA), PROCEEDINGS OF TECHNICAL PAPERS | 2006年

关键词：

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

We demonstrate for the first time the integration of metal gate electrode and non-melt laser annealed junctions in both NMOS and PMOS transistors. We report the highest drive current so far in laser annealed devices with good Short Channel Effects (SCE) control down to 40nm gate length. Overlap length is quantified by CV and SSRM, values of 2 nm for both NMOS and PMOS laser-annealed transistors are reported for the first time.

引用

页码：119 / +

页数：2

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