Evaluation of various node configurations for fine-grain multithreading on stock processors

被引：1
|
作者：
Kim, JS
Ha, SH
Jhon, CS
机构：
来源：
HIGH PERFORMANCE COMPUTING ON THE INFORMATION SUPERHIGHWAY - HPC ASIA '97, PROCEEDINGS | 1997年
关键词：
D O I：
10.1109/HPC.1997.592172
中图分类号：
TP [自动化技术、计算机技术];
学科分类号：
0812 ;
摘要：
It becomes more and more interesting to construct multithreaded parallel machines using stock processors due to their high performance/price ratio. However no quantitative analysis has been reported on the effectiveness of various node configurations and its impact on the overall performance. In this paper we explore three different node configurations in detail and compare their dynamic characteristics through the instruction-level simulation with six benchmark programs. Our experiments show that employing a dedicated processor for communication and synchronization is a reasonable approach because it can almost double the performance. Several factors that limit the overall speedup are also presented.
引用
收藏
页码：349 / 354
页数：6
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