Development of timing driven IP design flow based on physical knowledge synthesis

Over the last three years, many of the big vendors in electronic design automation have focused their R&D efforts on all-in-one RTL-to-GDSII tool suites that tie together logical or register-transfer-level design and synthesis with floor planning-placement and routing. The idea is that linking these tools tightly in a single flow will better equip engineers to deal with the timing, power and signal-integrity issues of deep-submicron fabrication processes by letting them write RTL and perform synthesis, placement and routing in a single pass. The result is to get designs out of the door more quickly. Recent CAD methodologies such as SP&R from Cadence have made an attempt to address issues of timing closures and design reliability both of which are gaining significance as device geometries continues to shrink further into the deep submicron realm. Addressing these issues requires new levels of integration between logic design and physical implementation technologies. This paper proposes a Timing Driven IP design flow based on PKS technology. The study progressed with the development of script files for efficient timing. The preliminary results indicate 5% efficiency in the timing.