A design flow for multiplierless linear-phase FIR filters: From system specification to Verilog code

被引：0

作者：

Jheng, KY ^{[1
]}

Jou, SJ ^{[1
]}

Wu, AY ^{[1
]}

机构：

[1] Natl Taiwan Univ, Grad Inst Elect Engn, Taipei 106, Taiwan

来源：

2004 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL 5, PROCEEDINGS | 2004年

关键词：

D O I：

暂无

中图分类号：

TP18 [人工智能理论];

学科分类号：

081104 ; 0812 ; 0835 ; 1405 ;

摘要：

This paper presents a design flow for the multiplierless linear-phase FIR filter synthesizer, which combines several research efforts. We propose a local search algorithm with variable filter order to reduce the number of adders further. In addition, several design techniques are adopted to reduce the hardware complexity of the system. By using this synthesizer, the system designers can design a filter efficiently and a chip can be successfully finished in a very short time.

引用

页码：293 / 296

页数：4

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