Multilevel QAM demodulator VLSI with wideband carrier recovery and dual equalizing mode

被引:17
|
作者
Yamanaka, K
Takeuchi, S
Murakami, S
Koyama, M
Ido, J
Fujiwara, T
Hirano, S
Okada, K
Sumi, T
机构
[1] System LSI Laboratory, Mitsubishi Electric Corp., Itami, Hyogo
[2] Osaka Prefecture University, Osaka
[3] LSI Laboratory, Mitsubishi Electric Corporation, Itami
[4] System LSI Laboratory, Mitsubishi Electric Corporation, Itami
[5] Inst. Electronics, Info. Commun. E.
[6] Nagaoka University of Technology, Nagaoka
[7] Kyoto University, Kyoto
[8] University of California, Los Angeles, CA
[9] Osaka University, Osaka
[10] Matsushita Electric Corporation, Moriguchi
[11] Custom LSI Designing Center, Mitsubishi Electric Corporation, Kamakura
[12] Inst. Electronics, Info. Commun. E., Inst. Television Engineers of Japan
[13] Kyoto Institute of Technology, Kyoto
[14] Doshisha University, Kyoto
[15] Utah State University, Logan, UT
[16] System LSI Laboratory, Mitsubishi Electric Corporation
[17] Kita-Itami Works, Mitsubishi Electric Corporation, Itami
关键词
equalizers; large-scale integration; phase detection; quadrature amplitude modulation; wire communication;
D O I
10.1109/4.597300
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
A 16-/64-/256-quadrature amplitude modulation (QAM) demodulator LSI with an all-digital carrier-recovery loop including a novel phase detector and a fractionally/symbol-spaced equalizer is described. The phase detector, which decides the transmitted symbol from received signal power, detects phase errors up to +/-45 degrees and enables the loop to internally eliminate the +/-80 kHz carrier-frequency offset. The fractionally spaced equalizer is implemented at the same clock rate as the symbol-spaced equalizer by increasing only mnltiplexers and flip-flops, though the former theoretically requires an operation twice as fast as the latter. A large scale integrator (LSI) operating at a symbol rate up to 8 MBaud is successfully implemented. The 0.5-mu m CMOS three-metal technology is used to implement 880 000 transistors in a die size of 12.87 x 12.49 mm(2).
引用
收藏
页码:1101 / 1107
页数:7
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