Assertions targeting a diverse set of verification tools

A myriad of proprietary (i.e., commercial tool specific) verification assertion languages exist today. These languages emerged due to the lack of formal language constructs supporting assertion specification in today's hardware description languages (HDL). The method described in this paper presents a unique process for unifying (or neutralizing the effects of) the many proprietary languages by using a set of predefined specification modules instantiated as assertions within the designer's HDL. This methodology creates numerous advantages and precludes the need to introduce new HDL constructs (i.e., extensions to Verilog are not required). It enables the design engineer to "specify once," then leverage the same HDL assertion specification over multiple verification processes - such as traditional simulation, semi-formal, and formal verification tools. It also eliminates the need for the design engineer to master tool specific and proprietary language details. Furthermore, this methodology enables evaluating new verification processes and tools (containing their own proprietary languages) seamlessly for the duration of the project, without the need to modify the original HDL text.