A novel DC-DC switched capacitor based voltage multiplier

An improved voltage multiplier stage is proposed which exhibits output impedance of 5 K Omega at input supply of 1.8 V and operating frequency of 100 MHz. Furthermore, 6-stage regulated charge pump is also designed using the proposed voltage multiplier cell to generate output voltage having magnitude of 10 V and deliver current load of 300 mu A during NonVolatile-Memory program/erase operation. The designed charge pump exhibits power efficiency of 48% at input supply of 1.8 V and operating frequency of 100 MHz while providing the current load of 300 mu A. The VCO based regulation scheme is employed in regulation loop of charge pump which minimize the ripple on output to 24 mV for 10 pF of capacitive load (contributed by nwell of NVM memory array). The proposed circuit is designed and simulated in 110 nm triple well CMOS technology employing only low voltage transistors and digital input supply of 1.8 V to validate its performance parameters.