Design of squarers modulo A with low-level pipelining

A squarer mod A is a circuit that computes the residue of the square of an integer X taken modulo a positive integer A. It is an essential building block in a variety of high-speed hardware for a digital signal processor (DSP) using residue number system (RNS) which implements, e.g., the quarter-square modulo multiplication, the squared Euclidean distance, the correlation, and circular convolution. Also, it is used to build large modulo exponentiators needed for implementation of cryptographic algorithms. In this paper, a comprehensive study of new squarers mod A is presented. For some special cases of A, like 2(alpha) - 1, 2(alpha), 2(alpha-1) + 1, and others, the general design approach is presented, which takes advantage of the periodicity of the series of powers of 2 taken modulo A, with no limitations on the size of A. The resulting squarers are almost exclusively composed of full- and half-adders which makes them suitable for low-level pipelining. For many A less than or equal to 64, the minimized logic functions of the squarers with small delay are also derived.