Performance Analysis of Scaler SoC for 4K Video Signal

This paper considers some issues to implement the scaler SoC. Because the size and power of SoC are constrained, the bit number to represent the coefficients of scaler kernel and LPF should be limited. In addition, the interpolation position should be located at the quantized phases. We analyze the effects of the various constraints in the performance of scaling system. The simulation results provide the guidance to implement the scaler SoC.