Multi-pin Optimization of Decoupling Capacitors on Practical Printed Circuit Boards

被引：0

作者：

Erdin, Ihsan ^{[1
]}

Achar, Ram ^{[2
]}

机构：

[1] Celestica Inc, Engn Design Serv, Ottawa, ON, Canada

[2] Carleton Univ, Dept Elect, Ottawa, ON, Canada

来源：

2018 IEEE ELECTRICAL DESIGN OF ADVANCED PACKAGING AND SYSTEMS SYMPOSIUM (EDAPS 2018) | 2018年

关键词：

Power delivery network (PDN); decoupling capacitors; power integrity; DESIGN;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A fast and efficient method is proposed for placement of decoupling capacitors on printed circuit boards (PCB) with resonant parallel planes. Using the pin impedance as a fitness function, a genetic algorithm (GA) based method is used for simultaneous optimization of capacitors' placement with respect to ball-grid array (BGA) pin fields. The proposed method applies to practical PCB designs without restriction on the number of power pins or planar geometry. The developed algorithm is tested on an industrial example in comparison to a numerical electromagnetic (EM) simulator. The results are shown to agree well while significant speed-up is obtained with the proposed algorithm.

引用

页数：3

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