Design of A 26GHz Phase-Locked Frequency Synthesizer in 0.13um CMOS

被引：0
|
作者：
Chen Yueyang [1 ]
Zhong Shun'an [1 ]
Dang Hua [1 ]
机构：
[1] Beijing Inst Technol, Dept Elect Engn, Sch Informat Sci & Technol, Beijing 10081, Peoples R China
来源：
2009 WRI INTERNATIONAL CONFERENCE ON COMMUNICATIONS AND MOBILE COMPUTING: CMC 2009, VOL 2 | 2009年
关键词：
Phase-locked loop; frequency synthesizer; high-speed; CMOS;
D O I：
10.1109/CMC.2009.213
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
A 26GHz Phase-Locked Frequency Synthesizer in 0.13um CMOS process is designed. This frequency synthesizer generates quadrature outputs at 26GHz. The PLL utilizing a QVCO with tuning range from 23.75GHz to 28.25GHz can he locked from 24GHz to 28GHz. The power consumption of the circuit is 34mW with a power supply of 1.2V. The phase noise of the QVCO is -95dBc/Hz at 1MHz offset and the Q-mismatch is 1.7 degrees. Circuits are simulated by Cadence Spectre in 0.13 mu m Standard CMOS Process.
引用
收藏
页码：541 / 544
页数：4
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