Low power array multiplier design by topology optimization

Left-to-right (L-R) linear array multiplication provides an interesting alternative to the conventional right-to-left (R-L) array multiplication as IR computation has the potential of saving power and delay. This paper presents topology optimization techniques for low-power IR array multipliers. These techniques include: interconnect reorganization, addition modules other than 3-to-2 carry save adders for PP reduction, and split array architectures. Our experiments indicate that interconnect reorganization can be a primary choice for L-R array multipliers if power is the critical concern. L-R schemes with optimized interconnect achieve the least power consumption in most cases with relatively small delay. When small power-delay product is the main goal, the more complex split array architectures are good candidates.