Design and tests of solid-state fault current limiters prototypes

The fault current level in distribution systems has increased in the last years mainly due to the energy consumption is in the limit of the production capacity and also the insertion of distributed generation, since the short circuits happen very closer to the generators now. In addition to this, most of the power substations were designed decades ago, so their equipment is overcome, and they may be damaged in a fault occurrence. To effectively protect the settled equipment or to avoid high investment costs in replacing them, one possible solution is to install a solid-state fault current limiter (SSFCL), which may reduce the fault current to a value under the supported level. In this context, this work proposes the development of two kinds of SSFCLs: series-switched reactor and resonant circuit. These devices were designed and compared experimentally in bench prototypes. The measurements showed that both topologies could reduce the fault current from 600 A(PEAK) to 75 A(PEAK). Both SSFCL-tested configurations were implemented using silicon controlled rectifier or insulated gate bipolar transistor. The results present the comparison between them, showing the impact in the first semi-cycle current profile, depending on the type of semiconductor switch adopted. This article also proposes a fault detection algorithm evaluated through digital implementation in a microcontroller. The algorithm detects the fault by the instantaneous current value and its derivative, using a control strategy that avoids false detection due to measurement noises. The theoretical analysis and results are useful contributions to support the SSFCL topology choice regarding its application.