Flexible-Assignment Calibration Technique for Mismatch-Constrained Digital-to-Analog Converters

This paper presents a calibration technique for mismatch-constrained digital-to-analog converters (DACs). The architecture is based on a fully flexible unit current cell assignment. The calibration is performed in a highly digital manner and does not require adjustment of on-chip analog voltages. The method significantly improves low-frequency linearity of the DAC with low hardware overhead and is ideally applicable to low-frequency calibration or dc-trimming DACs. This paper proposes multitude of algorithms that seek to assign the unit cells to minimize the residual error along with tradeoffs between achievable accuracy and calibration complexity in the algorithms. To validate the proposed calibration method, a prototype current-steering DAC has been implemented in 90-nm/1.2 V CMOS technology. The implementation is highly regular, making it suitable for the restrictive design rules of deep sub micron process technologies. The experimental result shows that more than 3-b of linearity improvement is achieved by applying the proposed calibration technique, showing that substantial net area saving is possible in comparison with the brute-force sizing method.