A Wide-range Low Power Quarter Rate Single Loop CDR

This paper presents a reference-less single loop clock and data recovery circuit (CDR). The proposed CDR is operating with unlimited capture range. And problem generated by oversampling is removed using bang-bang phase detector (BBPD) with two samples per 1UI. Simulation result shows the proposed CDR achieves a wide capture range from 2.6Gb/s to 13.2Gb/s and power consumption is 0.363 [pJ/bit] at 13.2Gb/s. This work is designed using 28nm CMOS process.