共 50 条
- [32] Design of low-power high-speed maximum a priori decoder architectures DESIGN, AUTOMATION AND TEST IN EUROPE, CONFERENCE AND EXHIBITION 2001, PROCEEDINGS, 2001, : 258 - 265
- [33] Racetrack Memory-based Encoder/Decoder for Low-Power Interconnect Architectures PROCEEDINGS OF 2016 INTERNATIONAL CONFERENCE ON EMBEDDED COMPUTER SYSTEMS: ARCHITECTURES, MODELING AND SIMULATION (SAMOS), 2016, : 281 - 287
- [35] Low-power saturated arithmetic and its application in VLSI architectures for OFDM modems 2006 IEEE WORKSHOP ON SIGNAL PROCESSING SYSTEMS DESIGN AND IMPLEMENTATION, 2006, : 200 - 204
- [36] Fast-Converging and Low-Power LDPC Decoding: Algorithm, Architecture, and VLSI Implementation Journal of Signal Processing Systems, 2021, 93 : 1271 - 1286
- [37] Fast-Converging and Low-Power LDPC Decoding: Algorithm, Architecture, and VLSI Implementation JOURNAL OF SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY, 2021, 93 (11): : 1271 - 1286
- [38] A VLSI implementation of an adaptive-effort low-power Viterbi decoder for wireless communications CANADIAN CONFERENCE ON ELECTRICAL AND COMPUTER ENGINEERING 2001, VOLS I AND II, CONFERENCE PROCEEDINGS, 2001, : 1183 - 1188
- [40] A high-speed fully-programmable VLSI decoder for regular LDPC codes 2006 IEEE INTERNATIONAL CONFERENCE ON ACOUSTICS, SPEECH AND SIGNAL PROCESSING, VOLS 1-13, 2006, : 3423 - 3426