Voltage comparator circuits for multiple-valued CMOS logic

A new voltage-mode comparator circuit for use in CMOS multiple-valued logic circuits is introduced Existing comparator circuits for this application use static current or clocking and thus consume static power or clocking power. In order to reduce these power requirements, we have examined static circuit designs that eliminate DC current paths when the inputs and outputs are at logical values. Elimination of DC current paths requires increased circuit complexity, layout area, and signal delay. This paper proposes comparator circuits that use static logic circuits and thus require no static current and no static (DC) power. HSPICE simulations of these circuits using model parameter values for a 0.35-mum n-well CMOS technology and a 3.3 volt power supply show that each of these comparator circuits consumes static power on the order of nWs. Simulations with the model parameter values for the thick-oxide (5-volt) option of the 0.35-mum technology and for a 1.2-mum (5-volt) CMOS technology are also presented. These power levels are consistent with those of standard binary CMOS logic circuits in the same technologies.