Triple transistor based triple modular redundancy with embedded voter circuit

This paper presents a new static redundancy technique that combines the redundancy at transistor level with redundancy at functional level and offers a very good reliability at minimal increase in the hardware, delay and power overheads. The proposed method does not require any external voter hardware as in triple modular redundancy (TMR) method; instead the last level gates of the triplicated modules of the circuit are combined and designed using fault tolerant triple transistor logic which act as an embedded voter circuit. This method offers higher reliability at lesser area and shorter critical path compared to the most popular TMR method as well as other recently proposed static fault tolerant methods. This makes our design suitable for designing fault tolerant systems for real-time resource constrained applications. We have provided theoretical analysis as well as simulation results proving the superiority of our method.