Hardware-software partitioning of real-time operating systems using Hopfield neural networks

被引:7
|
作者
Guo, Bing [1 ]
Wang, Dianhui
Shen, Yan
Liu, Zhong
机构
[1] Sichuan Univ, Sch Comp Sci & Engn, Chengdu 610065, Peoples R China
[2] La Trobe Univ, Dept Comp Sci & Comp Engn, Melbourne, Vic 3086, Australia
[3] Univ Elect Sci & Technol China, Sch Mechatron Engn, Chengdu 610054, Peoples R China
[4] Sichuan Architecture Profess Technol Coll, Deyang 618000, Peoples R China
基金
中国国家自然科学基金;
关键词
Hopfield neural network; hardware-software partitioning; real-time operating system; system-on-a-chip;
D O I
10.1016/j.neucom.2006.02.012
中图分类号
TP18 [人工智能理论];
学科分类号
081104 ; 0812 ; 0835 ; 1405 ;
摘要
The hardware-software automated partitioning of a real-time operating system in the system-on-a-chip (SoC-RTOS partitioning) is a NP-complete problem, and a crucial step in the hardware-software co-design of SoC. In this paper, a new model for SoC-RTOS partitioning is introduced, which can help in understanding the essence of the SoC-RTOS partitioning. A discrete Hopfield neural network approach for implementing the SoC-RTOS partitioning is proposed, where a novel energy function, operating equation and coefficients of the neural network are redefined. Simulations are carried out with comparison to other optimization techniques. Experimental results demonstrate the feasibility and effectiveness of the proposed method. (c) 2006 Elsevier B.V. All rights reserved.
引用
收藏
页码:2379 / 2384
页数:6
相关论文
共 50 条
  • [41] CxDNN: Hardware-software Compensation Methods for Deep Neural Networks on Resistive Crossbar Systems
    Jain, Shubham
    Raghunathan, Anand
    [J]. ACM TRANSACTIONS ON EMBEDDED COMPUTING SYSTEMS, 2020, 18 (06)
  • [42] Hardware Support for Resource Partitioning in Real-Time Embedded Systems
    Honmura, Tetsuro
    Kondoh, Yuki
    Yamada, Tetsuya
    Takada, Masashi
    Nitoh, Takumi
    Nojiri, Tohru
    Toyama, Keisuke
    Saitoh, Yasuhiko
    Nishi, Hirofumi
    Sato, Mikiko
    Namiki, Mitaro
    [J]. 2013 IEEE COOL CHIPS XVI (COOL CHIPS), 2013,
  • [43] Hardware/software partitioning of core-based systems using pulse coupled neural networks
    Chang, Zhengwei
    Xiong, Guangze
    [J]. ADVANCES IN NEURAL NETWORKS - ISNN 2007, PT 3, PROCEEDINGS, 2007, 4493 : 1015 - +
  • [44] Hardware-software cosynthesis of multi-mode multi-task embedded systems with real-time constraints
    Oh, H
    Ha, S
    [J]. CODES 2002: PROCEEDINGS OF THE TENTH INTERNATIONAL SYMPOSIUM ON HARDWARE/SOFTWARE CODESIGN, 2002, : 133 - 138
  • [45] Safety Validation of an Embedded Real-Time System at Hardware-Software Integration Test Environment
    Philip, Gracy
    D'Souza, Meenakshi
    [J]. ADVANCED COMPUTING AND COMMUNICATION TECHNOLOGIES, 2016, 452 : 51 - 58
  • [46] Integrating real-time inter-task communication channels into hardware-software codesign
    Tak, Sungwoo
    Kim, Taehoon
    Park, E. K.
    [J]. MICROPROCESSORS AND MICROSYSTEMS, 2010, 34 (06) : 182 - 199
  • [47] Partitioning of hardware-software embedded systems: A metrics-based approach
    Balboni, A
    Fornaciari, W
    Sciuto, D
    [J]. INTEGRATED COMPUTER-AIDED ENGINEERING, 1998, 5 (01) : 39 - 55
  • [48] Hardware-Software Codesign of Automatic Speech Recognition System for Embedded Real-Time Applications
    Cheng, Octavian
    Abdulla, Waleed
    Salcic, Zoran
    [J]. IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, 2011, 58 (03) : 850 - 859
  • [49] Hardware-software partitioning for the design of system on chip by neural network optimization method
    Pan, Zhongliang
    Li, Wei
    Shao, Qingyi
    Chen, Ling
    [J]. SEVENTH INTERNATIONAL SYMPOSIUM ON PRECISION ENGINEERING MEASUREMENTS AND INSTRUMENTATION, 2011, 8321
  • [50] Specific features in building hardware-software complexes operating in real-time: An example of test rig used in periodic tests of reducers
    A. A. Urakov
    M. A. Rylov
    D. S. Shutov
    P. G. Dorofeev
    [J]. Automation and Remote Control, 2011, 72 : 1127 - 1133