Future SOC design challenges and solutions

被引：4

作者：

Chen, CCP ^{[1
]}

Cheng, E ^{[1
]}

机构：

[1] Univ Wisconsin, Dept Elect & Comp Engn, Madison, WI 53706 USA

来源：

PROCEEDING OF THE 2002 3RD INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN | 2002年

关键词：

D O I：

10.1109/ISQED.2002.996800

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

SOC (System on a Chip) design creates tremendous design challenges to the traditional VLSI ASIC design. It covers not only the traditional DSM (Deep Sub-Micron) issues but also the integration issues such as IP and signal integrity especially for integrated digita/analog system such as Bluetooth. Besides, power consumption and power delivery are also impose huge design constraints to the already difficult situation especially for the portable and mobile devices. This talk will introduce and analysis the potential SoC issues and potential solutions from the architecture level to the circuit level.

引用

页码：534 / 537

页数：4

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