Hierarchical fault tolerance for nanoscale memories

This paper considers dynamic fault tolerance techniques applicable to ultradense memories based on nanoscale crossbar architectures. It describes how they can be integrated, in a hierarchical fashion, to provide runtime protection against device failures. Simulation is employed to estimate the effectiveness of a number of configurations, and the results show that there are synergistic combinations that allow for substantial reliability improvements over conventional techniques. For example, a memory With a bit-level failure rate of 2 x 10(-4) FIT and a failure distribution of 10% arrays and 30% each for bits, rows, and columns shows three orders of magnitude reduction in uncorrectable errors at 100000 hours when a given amount of redundancy is allocated to a combination of error correction coding and spare rows, columns, and arrays versus other configurations.