Fault-tolerance of spaceborne Semiconductor Mass Memories

被引：7

作者：

Fichna, T ^{[1
]}

Gartner, M ^{[1
]}

Gliem, F ^{[1
]}

Rombeck, F ^{[1
]}

机构：

[1] Tech Univ Braunschweig, Inst Datenverarbeitungsanlagen, D-3300 Braunschweig, Germany

来源：

TWENTY-EIGHTH ANNUAL INTERNATIONAL SYMPOSIUM ON FAULT-TOLERANT COMPUTING, DIGEST PAPERS | 1998年

关键词：

D O I：

10.1109/FTCS.1998.689492

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

The architecture of spaceborne Semiconductor Mass Memories is mainly determined by the requirements on reliability and data integrity. The highly granular structure of the memory kernel supports the implementation of hierarchical redundancy structures. Error correcting codes are in use to cope with particle induced bit errors. For protection of 4-bit wide devices an extended Reed-Solomon (78,64) SSC DSD code is appropriate and well suited to a low expenditure H/W implementation of coding and checking.

引用

页码：408 / 413

页数：6

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