Unit testing based approach for reconfigurable logic controllers verification

被引:0
|
作者
Doligalski, Michal [1 ]
Tkacz, Jacek [1 ]
Bukowiec, Arkadiusz [1 ]
Gratkowski, Tomasz [1 ]
机构
[1] Univ Zielona Gora, Inst Comp Engn & Elect, Ul Licealna 9, PL-65417 Zielona Gora, Poland
关键词
FPGA; partial reconfiguration; state machine; rapid prototyping; quality; verification; simulation; IMPLEMENTATION;
D O I
10.1117/12.2205922
中图分类号
O43 [光学];
学科分类号
070207 ; 0803 ;
摘要
The paper presents unit testing-based approach to FPGA design in-circuit verification. Presented methodology is dedicated to modular reconfigurable logic controllers, but other ip-cores and systems can be verified as well. The speed and reproducibility of tests is key for rapid system prototyping, where the quality and reliability of the system is significance. Typically FPGA are programmed by means single (full) bitstream. Specific devices are able to be reconfigured partially. Usually the partial reconfiguration is a part of the design functionality. It enables the minimization of used resources or provides specific functionality like system adaptation. The paper presents the use of the partial reconfiguration as a toll for the designer. The unit testing approach well know form software engineering was adopted to modular logic controllers development. The simulation process results waveform files, the waveform can be used for synthesizable test bench generation.
引用
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页数:9
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