A Unified Formal Model for Proving Security and Reliability Properties

Taint-propagation and X-propagation analyses are important tools for enforcing circuit design properties such as security and reliability. Fundamental to these tools are effective models for accurately measuring the propagation of information and calculating metadata. In this work, we formalize a unified model for reasoning about taint- and X-propagation behaviors and verifying design properties related to these behaviors. Our model are developed from the perspective of information flow and can be described using standard hardware description language (HDL), which allows formal verification of both taint-propagation (i.e., security) and X-propagation (i.e., reliability) related properties using standard electronic design automation (EDA) verification tools. Experimental results show that our formal model can be used to prove both security and reliability properties in order to uncover unintended design flaw, timing channel and intentional malicious undocumented functionality in circuit designs.