Probabilistic testability measure before pseudorandom test generation

被引:0
|
作者
Kaminska, M. O. [1 ]
Kulak, E. N. [1 ]
Guz, O. A. [1 ]
Yeliseev, V. V. [2 ]
机构
[1] Kharkov Natl Univ Radio Elect, Design Automat Dept, UA-61166 Kharkov, Ukraine
[2] N Donetsk Technol Univ, UA-93400 Kharkov, Ukraine
来源
PROCEEDINGS OF THE INTERNATIONAL CONFERENCE MIXED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS | 2006年
关键词
controllability; observability; testability; probability;
D O I
10.1109/MIXDES.2006.1706649
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
It is proposed more suitable method of the testability analysis of the digital systems in comparison with known classical algorithmic and probabilistic methods. It is oriented on the complex combinational and sequential asynchronous logic circuits. Estimation of the testability is based on the topological analysis of the circuit. The new method and above mentioned methods were approved on the circuits of different complexity, including circuits from ISCAS'85, '89 Libraries. Proposed method can be used on gate-level and RT-level circuit description. http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=1706649
引用
收藏
页码:591 / +
页数:2
相关论文
共 50 条
  • [1] TESTABILITY MEASURE TO IMPROVE ALGEBRAIC TEST GENERATION.
    Lioy, Antonio
    Mezzalama, Marco
    Software & microsystems, 1984, 3 (02): : 37 - 41
  • [2] Combined probabilistic testability calculation and compact test generation for PLAs
    Reppen, Bjorg
    Aas, Einar J.
    Journal of Electronic Testing: Theory and Applications (JETTA), 1991, 2 (03): : 215 - 227
  • [3] TESTABILITY MEASURES IN PSEUDORANDOM TESTING
    ERCOLANI, S
    FAVALLI, M
    DAMIANI, M
    OLIVO, P
    RICCO, B
    IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 1992, 11 (06) : 794 - 800
  • [4] DIGITAL TEST-GENERATION AND DESIGN FOR TESTABILITY
    GRASON, J
    NAGLE, AW
    JOURNAL OF DIGITAL SYSTEMS, 1981, 5 (04): : 319 - 359
  • [5] CONCURRENT TEST-GENERATION AND DESIGN FOR TESTABILITY
    CHENG, KT
    AGRAWAL, VD
    1989 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-3, 1989, : 1935 - 1938
  • [6] EXPERIMENTAL EVALUATION OF TESTABILITY MEASURES FOR TEST-GENERATION
    CHANDRA, SJ
    PATEL, JH
    IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 1989, 8 (01) : 93 - 97
  • [7] A new design flow and testability measure for the generation of a structural test and BIST for analogue and mixed-signal circuits
    Hoffmann, C
    DESIGN, AUTOMATION AND TEST IN EUROPE CONFERENCE AND EXHIBITION, 2002 PROCEEDINGS, 2002, : 197 - 204
  • [8] Hierarchical test generation and design for testability of ASPPs and ASIPs
    Ghosh, I
    Raghunathan, A
    Jha, NK
    DESIGN AUTOMATION CONFERENCE - PROCEEDINGS 1997, 1997, : 534 - 539
  • [9] CMOS FAULT MODELING, TEST-GENERATION AND DESIGN FOR TESTABILITY
    MATTHAUS, C
    KRUGERSPRENGEL, B
    GLOWACZ, C
    HUBNER, U
    VIERHAUS, HT
    MICROPROCESSING AND MICROPROGRAMMING, 1988, 24 (1-5): : 233 - 238
  • [10] An effective design for hierarchical test generation based on strong testability
    Ichihara, H
    Okamoto, N
    Inoue, T
    Hosokawa, T
    Fujiwara, H
    14TH ASIAN TEST SYMPOSIUM, PROCEEDINGS, 2005, : 288 - 293