A 1.2 ps-Jitter Fully-Synthesizable Fully-Calibrated Fractional-N Injection-Locked PLL Using True Arbitrary Nonlinearity Calibration Technique

被引：0

作者：

Liu, Bangan ^{[1
]}

Ngo, Huy Cu ^{[1
]}

Nakata, Kengo ^{[1
]}

Deng, Wei ^{[1
]}

Zhang, Yuncheng ^{[1
]}

Qiu, Junjun ^{[1
]}

Yoshioka, Toru ^{[1
]}

Emmei, Jun ^{[1
]}

Zhang, Haosheng ^{[1
]}

Pang, Jian ^{[1
]}

Narayanan, Aravind Tharayil ^{[1
]}

Yang, Dongsheng ^{[1
]}

Liu, Hanli ^{[1
]}

Okada, Kenichi ^{[1
]}

Matsuzawa, Akira ^{[1
]}

机构：

[1] Tokyo Inst Technol, Dept Elect & Elect Engn, Meguro Ku, 2-12-1-S3-27 Ookayama, Tokyo 1528552, Japan

来源：

2018 IEEE CUSTOM INTEGRATED CIRCUITS CONFERENCE (CICC) | 2018年

关键词：

fully-synthesizable; digital PLL; injection-locked PLL; DTC calibration;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents a fully-synthesizable fractional-N injection-locked PLL in 65 nm CMOS. A true arbitrary non-linearity calibration scheme is specifically proposed for synthesizable DTC, together with an extensive digital calibration of the PLL. The RMS jitter of 1.2 ps and 0.3 ps is achieved at 1 GHz output for fractional-N and integer-N operation, respectively. The power consumption is 2.5 mW and 2.2 mW, corresponding to an FoM of -234.4 dB and -246.7 dB.

引用

页数：4