A Fully-Synthesizable Fractional-N Injection-Locked PLL for Digital Clocking with Triangle/Sawtooth Spread-Spectrum Modulation Capability in 5-nm CMOS

被引：16

作者：

Liu, Bangan ^{[1
]}

Zhang, Yuncheng ^{[1
]}

Qiu, Junjun ^{[1
]}

Huang, Hongye ^{[1
]}

Sun, Zheng ^{[1
]}

Xu, Dingxin ^{[1
]}

Zhang, Haosheng ^{[1
]}

Wang, Yun ^{[1
]}

Pang, Jian ^{[1
]}

Li, Zheng ^{[1
]}

Fu, Xi ^{[1
]}

Shirane, Atsushi ^{[1
]}

Kurosu, Hitoshi ^{[2
]}

Nakane, Yoshinori ^{[2
]}

Masaki, Shunichiro ^{[2
]}

Okada, Kenichi ^{[1
]}

机构：

[1] Tokyo Inst Technol, Dept Elect & Elect Engn, Tokyo 1528550, Japan

[2] Socionext Inc, Yokohama, Kanagawa 2220033, Japan

来源：

IEEE SOLID-STATE CIRCUITS LETTERS | 2020年 / 3卷

关键词：

Fully synthesizable; injection locking; phase-locked loop (PLL); ring oscillator (RO); spread-spectrum clocking (SSC);

D O I：

10.1109/LSSC.2020.2967744

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

A fully synthesizable injection-locked phase-locked loop (IL-PLL) for digital clocking is proposed in this letter. The phase-locked loop (PLL) is implemented in a 5-nm CMOS process, with only digital standard cells are used. With proposed triple-path operation and digital offset control for digital-to-time converter (DTC), low-jitter fractional-N frequency synthesis, and highly-linear spread-spectrum clocking are realized with low-power consumption. The PLL core area is 0.0036 mm(2). With 100-MHz reference frequency, better than -234.7 dB figure-of-merit (FOM) is achieved in the fractional-N mode, with -44.3 dBc worst-case fractional spur. The proposed PLL has the smallest chip area, highest FOM, and lowest fractional spur among ring oscillator (RO)-based fractional-N PLLs in sub-20-nm processes.

引用

页码：34 / 37

页数：4

共 3 条

[1] A 1.2 ps-Jitter Fully-Synthesizable Fully-Calibrated Fractional-N Injection-Locked PLL Using True Arbitrary Nonlinearity Calibration Technique
Liu, Bangan
Ngo, Huy Cu
Nakata, Kengo
Deng, Wei
Zhang, Yuncheng
Qiu, Junjun
Yoshioka, Toru
Emmei, Jun
Zhang, Haosheng
Pang, Jian
Narayanan, Aravind Tharayil
Yang, Dongsheng
Liu, Hanli
Okada, Kenichi
Matsuzawa, Akira
2018 IEEE CUSTOM INTEGRATED CIRCUITS CONFERENCE (CICC), 2018,
[2] An Injection-Locked Ring-Oscillator-Based Fractional-N Digital PLL Supporting BLE Frequency Modulation
He, Yuming
van den Heuvel, Johan
Mateman, Paul
Allebes, Erwin
Traferro, Stefano
Dijkhuis, Johan
Bunsen, Keigo
Vis, Peter
Breeschoten, Arjan
Liu, Yao-Hong
Matsumoto, Tomohiro
Bachmann, Christian
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2022, 57 (06) : 1765 - 1775
[3] A Fractional-N, All-digital Injection-Locked PLL with Wide Tuning Range Digitally Controlled Ring Oscillator and Bang-Bang Phase Detection for Temperature Tracking in 40nm CMOS
Grollitsch, Werner
Nonis, Roberto
ESSCIRC CONFERENCE 2016, 2016, : 201 - 204

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