Improving the Fault Tolerance in Multistage Interconnection Networks

The high-performance computing is a key component that drives the current society. In these systems, the interconnection network is a key piece to obtain not only a high performance but also the highest level of fault-tolerance. Indirect topologies are often chosen in the design of HPC systems. Although there is an endless number of topologies, the most commonly used is the fat-tree. This paper presents a proposal for a new network topology that provides a high fault-tolerance level and the possibility of reducing the HoL blocking while increasing the network performance, using the same hardware as the fat-tree one.