Design and implementation of the POWER5™ microprocessor

被引：1

作者：

Clabes, J ^{[1
]}

Friedrich, J ^{[1
]}

Sweet, M ^{[1
]}

DiLullo, J ^{[1
]}

Chu, S ^{[1
]}

Plass, D ^{[1
]}

Dawson, J ^{[1
]}

Muench, P ^{[1
]}

Powell, L ^{[1
]}

Floyd, M ^{[1
]}

Sinharoy, B ^{[1
]}

Lee, M ^{[1
]}

Goulet, M ^{[1
]}

Wagoner, J ^{[1
]}

Schwartz, N ^{[1
]}

Runyon, S ^{[1
]}

Gorman, G ^{[1
]}

Restle, P ^{[1
]}

Kalla, R ^{[1
]}

McGill, J ^{[1
]}

Dodson, S ^{[1
]}

机构：

[1] IBM Corp, Syst Grp, Austin, TX USA

来源：

2004 INTERNATIONAL CONFERENCE ON INTEGRATED CIRCUIT DESIGN AND TECHNOLOGY | 2004年

关键词：

D O I：

10.1109/ICICDT.2004.1309931

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

引用

页码：143 / 145

页数：3

共 50 条

[41] Design and implementation of the AMCC self-timed microprocessor in FPGAs
Ortega-Cisneros, Susana
Raygoza-Panduro, Juan Jose
Galvez, Alberto de la Mora
JOURNAL OF UNIVERSAL COMPUTER SCIENCE, 2007, 13 (03) : 377 - 387
[42] Design of asynchronous pipelines for low-power microprocessor
Shi, Wei
Wang, You-Rui
Chen, Fang-Yuan
Ren, Hong-Guang
Lu, Hong-Yi
Wang, Zhi-Ying
Guofang Keji Daxue Xuebao/Journal of National University of Defense Technology, 2009, 31 (05): : 33 - 37
[43] Design methodology for the IBM POWER7 microprocessor
Friedrich, J.
Puri, R.
Brandt, U.
Buehler, M.
DiLullo, J.
Hopkins, J.
Hossain, M.
Kazda, M.
Keinert, J.
Kurzum, Z. M.
Lamb, D.
Lee, A.
Musante, F.
Noack, J.
Osler, P. J.
Posluszny, S.
Qian, H.
Ramji, S.
Rao, V.
Reddy, L. N.
Ren, H.
Rosser, T.
Russell, B. R.
Sze, C.
Tellez, G.
IBM JOURNAL OF RESEARCH AND DEVELOPMENT, 2011, 55 (03)
[44] The circuit andphysical design of the POWER4 microprocessor
Warnock, JD
Keaty, JM
Petrovick, J
Clabes, JG
Kircher, CJ
Krauter, BL
Restle, PJ
Zoric, BA
Anderson, CJ
IBM JOURNAL OF RESEARCH AND DEVELOPMENT, 2002, 46 (01) : 27 - 51
[45] IBM POWER6 microprocessor physical design and design methodology
Berridge, R.
Averill, R. M., III
Barish, A. E.
Bowen, M. A.
Camporese, P. J.
DiLullo, J.
Dudley, P. E.
Keinert, J.
Lewis, D. W.
Morel, R. D.
Rosser, T.
Schwartz, N. S.
Shephard, P.
Smith, H. H.
Thomas, D.
Restle, P. J.
Ripley, J. R.
Runyon, S. L.
Williams, P. M.
IBM JOURNAL OF RESEARCH AND DEVELOPMENT, 2007, 51 (06) : 685 - 714
[46] The circuit and physical design of the POWER4 microprocessor
Warnock, J.D. (jwarnock@us.ibm.com), 1600, IBM Corporation (46):
[47] Principles for Implementation of Digital Power Direction Control in Microprocessor Current Protections
Romaniuk, F. A.
Rumiantsev, V. Yu.
Rumiantsev, Yu., V
Dziaruhina, A. A.
Klimkovich, P. I.
SCIENCE & TECHNIQUE, 2023, 22 (04): : 317 - 325
[48] Some issues of microprocessor-based power system stabilizer implementation
Tecec, Zlatka
Cesic, Vinko
Petrovic, Ivan
2007 MEDITERRANEAN CONFERENCE ON CONTROL & AUTOMATION, VOLS 1-4, 2007, : 412 - +
[49] Characterization of simultaneous verification multithreading (SMT) efficiency in POWER5 (vol 49, pg 555, 2005)
Mathis, HM
IBM JOURNAL OF RESEARCH AND DEVELOPMENT, 2005, 49 (06) : 1003 - 1003
[50] Design and implementation of a fully asynchronous SFQ microprocessor: SCRAM2
Nobumori, Yusuke
Nishigai, Takanobu
Nakamiya, Kazunori
Yoshikawa, Nobuyuki
Fujimaki, Akira
Terai, Hirotaka
Yorozu, Shinich
IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY, 2007, 17 (02) : 478 - 481

← 1 2 3 4 5 →