A thread partitioning algorithm in low power high-level synthesis

被引：2

作者：

Uchida, J ^{[1
]}

Togawa, N ^{[1
]}

Yanagisawa, M ^{[1
]}

Ohtsuki, T ^{[1
]}

机构：

[1] Waseda Univ, Dept Comp Sci, Tokyo 169, Japan

来源：

ASP-DAC 2004: PROCEEDINGS OF THE ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE | 2004年

关键词：

D O I：

10.1109/ASPDAC.2004.1337543

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper proposes a thread partitioning algorithm in low power high-level synthesis. The algorithm is applied to high-level synthesis systems. In the systems, we can describe parallel behaving circuit blocks(threads) explicitly. First it focuses on a local register file RF in a thread. It partitions a thread into two sub-threads, one of which has RF and the other does not have, RF. The partitioned sub-threads need to be synchronized with each other to keep the data dependency of the original thread. Since the partitioned sub-threads have waiting time for synchronization, gated clocks can be applied to each sub-thread. Then we can synthesize a low power circuit with a low area overhead, compared to the original circuit. Experimental results demonstrate effectiveness and efficiency of the algorithm.

引用

页码：74 / 79

页数：6

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