FPGA Implementation of a Novel Area Efficient FFT Scheme Using Mixed Radix FFT

In the literature, mixed radix FFT scheme has been proposed to facilitate the computation of FFT in parallel using multiple lower radix FFT modules. Alternately, the speed of the FFT can be increased using Radix-2 decimation-in-frequency (DIF) FFT algorithm with Multipath Delay Commutator (R2MDC) architecture. In this paper, a novel FFT scheme which combines the R2MDC architecture with the serial version of mixed radix FFT scheme is proposed. To study the efficacy of this approach, an 8-point FFT is implemented using R2MDC architecture. Using this, 16-point, 32-point and 64-point FFTs are realized with the serial version of mixed radix scheme and also using only R2MDC architecture on Xilinx Virtex-5 FPGA. From the implementation results, it is found that the hardware requirement for the proposed approach reduces by 25%-53% at the cost of speed compared to the other schemes reported in the literature including that using only R2MDC architecture. The proposed scheme is preferred for low sampling rate applications such as biomedical signal processing.