Quaternary Edge-Triggered Flip-Flop with Neuron-MOS Literal Circuit

A novel CMOS quaternary D-type edge-triggered flip-flop using a single latch with neuron-MOS literal circuits is presented. In the proposed circuit, data are sampled into the latch during a short transparency period for rising edge of the clock signal by using the arrow pulse produced by the race-hazard of the clock signal. The quaternary literal functions are realized by using neuron-MOS transistors without any modification of the thresholds. The benefit of the proposed voltage-mode quaternary flip-flop is that the circuit can be fabricated by standard CMOS process with a 2-ploy layer. Besides, it has a simpler construction with respect to previously reported quaternary flip-flop. The effectiveness of the proposed circuit has been validated by HSPICE simulation results with TSMC 0.35 mu m 2-ploy 4-metal CMOS technology.