2-D discrete wavelet transform implementation in FPGA device for real-time image processing

A new approach to FPGA implementation of two-dimensional discrete wavelet transform is presented. This architecture allow high accurate and sampling rate DWT realization based on FIR filters of substantial length to be implemented on current generation FPGAs. The scheme is based on two parallel pipelined linear phase 17-tap FIR filters with common shift register, partial adders and look-up tables as coefficient multipliers with 4-stage pipelined architecture. The transform is realized in three stages controlled by the state machine, where temporary (L and H) and final subimages (LL, LH, HL, and HH) are created. High throughput (1050 MIPS) and external memory controller allow efficient concurrent cooperation with external processors.