Acceleration of Genetic Algorithm based FPGA Placers using GPGPU

被引：0
|
作者：
Cheong, Ke You [1 ]
Panicker, Rajesh C. [1 ]
机构：
[1] Natl Univ Singapore, Dept Elect & Comp Engn, Singapore, Singapore
来源：
PROCEEDINGS OF THE 2016 IEEE REGION 10 CONFERENCE (TENCON) | 2016年
关键词：
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
With the scaling of process nodes, the complexity of IC design continues to increase. This increase in complexity greatly increases the time needed by many electronic design automation (EDA) tools to perform optimizations. Placer is one such tool that has been seeing a large increase in the time required for execution. Due to the large solution space and tight constraints, the amount of computations needed to arrive at a reasonably good solution increases exponentially. This work explores the acceleration of a genetic algorithm-based placer for field programmable gate arrays (FPGAs) using general-purpose computing on graphics processing units (GPGPUs).
引用
收藏
页码：3801 / 3804
页数：4
相关论文
共 50 条
  • [1] Compression acceleration using GPGPU
    Shastry, Krishnaprasad
    Pandey, Avinash
    Agrawal, Ashutosh
    Sarveswara, Ravi
    2016 23RD IEEE INTERNATIONAL CONFERENCE ON HIGH PERFORMANCE COMPUTING WORKSHOPS (HIPCW 2016), 2016, : 70 - 78
  • [2] Parallel acceleration of AES algorithm using FPGA
    Lu, LR
    Kuang, YH
    Yang, QH
    Cheng, SL
    DCABES 2001 PROCEEDINGS, 2001, : 242 - 245
  • [3] Acceleration of the Retinex algorithm for image restoration by GPGPU/CUDA
    Wang, Yuan-Kai
    Huang, Wen-Bin
    PARALLEL PROCESSING FOR IMAGING APPLICATIONS, 2011, 7872
  • [4] Research of FMM Algorithm Acceleration Based on FPGA and Cell BE
    Chai, Yahui
    Shen, Wenfeng
    Xu, Weimin
    Zheng, Yanheng
    EQUIPMENT MANUFACTURING TECHNOLOGY AND AUTOMATION, PTS 1-3, 2011, 317-319 : 1563 - 1567
  • [5] An FPGA-Based Acceleration Platform for Auction Algorithm
    Zhu, Pengfei
    Zhang, Chun
    Li, Hua
    Cheung, Ray C. C.
    Hu, Bryan
    2012 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS 2012), 2012, : 1002 - 1005
  • [6] An FPGA based adaptive genetic algorithm
    1829, Science Press, Beijing, China (27):
  • [7] Acceleration of Backtracking Algorithm with FPGA
    Kasik, Vladimir
    2010 INTERNATIONAL CONFERENCE ON APPLIED ELECTRONICS, 2010, : 149 - 152
  • [8] Acceleration of Game Tree Search Using GPGPU
    Mahale, Kajal
    Kanaskar, Shital
    Kapadnis, Prachi
    Desale, Madhuri
    Walunj, S. M.
    2015 INTERNATIONAL CONFERENCE ON GREEN COMPUTING AND INTERNET OF THINGS (ICGCIOT), 2015, : 550 - 553
  • [9] GPGPU Implementation of a Genetic Algorithm for Stereo Refinement
    Arranz, Alvaro
    Alvar, Manuel
    INTERNATIONAL JOURNAL OF INTERACTIVE MULTIMEDIA AND ARTIFICIAL INTELLIGENCE, 2015, 3 (02): : 69 - 76
  • [10] Implementation of a FPGA-based genetic algorithm
    Jisuanji Gongcheng, 9 (41-42, 48):
12345