A High-Speed CMOS Image Sensor With Column-Parallel Two-Step Single-Slope ADCs

This paper proposes a column-parallel two-step single-slope (SS) ADC for high-speed CMOS image sensors. Error correction scheme to improve the linearity is proposed as well. A prototype sensor of 321) x 240 pixels has been fabricated with a 0.35-mu m CMOS process. Measurement results demonstrate that the proposed ADC can achieve the conversion time of 4 mu s, which is ten times faster than the conventional SS ADC. The proposed error correction effectively removes the dead hand problem and yields DNL of +0.53/ -0.78 LSB and INI, of +1.42/ -1.61 LSB. The power consumption is 36 mW from a supply voltage of 2.8 V.