Design and Analysis of a Two-stage CMOS Op-amp using Silterra's 0.13 μm Technology

This paper presents the design and analysis of a high-gain, low-power, two-stage CMOS operational amplifier (op-amp) for a sigma-delta ADC. Op-amp topologies, such as folded cascade, telescopic and two-stage, are discussed in this paper. The theoretical and topological analyses of each design are highlighted in detail, including the trade-off among various parameters such as gain, noise, output swings and power consumption. The designs have been simulated using 0.13 mu m CMOS technology from Silterra (Malaysia) with Cadence FDA tools. From the simulation results, the two-stage amplifier gives better performance compared to other topologies, especially in terms of gain, output swing, slew rate and CMRR. The circuit is able to achieve 85.93 dB gain, a 1.1 V output swing, a 44.29 V/mu s slew rate and a CMRR of 61 dB with a power supply voltage of 1.2 V.