Specification and synthesis of Petri Net based reprogrammable logic controller

The goal of the paper is to present a novel approach to Application Specific Logic Controllers realisation, which is suitable especially for small, embedded system designs. A discrete model of Logic Controller is derived directly from Hierarchical Control Interpreted Petri Net or related Sequential Function Chart (SFC) and synthesised as a dedicated modular microsystem. The unified model is reflected in Programmable Logic. The desired behaviour of the designed logic controller can be validated by simulation in VHDL environment. The paper covers some effective techniques for computer-based synthesis of Reprogrammable Logic Controllers, from Petri net level to the logic design level. Copyright (C) 2001 IFAC.