MPEG-2 decoder implementation on MAP1000A mediaprocessor using the C language

Mediaprocessors offer several advantages over hardwired MPEG-2 decoder chips, such as the capability to perform multiple functions, update the algorithms and customize the system with enhanced features. MAP1000A is a highly integrated mediaprocessor platform with multiple processing units for parallel processing. The input bitstream is parsed and decoded by the VLX coprocessor, which is a small and fast processor designed for sequential operations. The decoded information is then passed to the VLIW Core that performs the pixel-intensive operations such as the inverse quantization, inverse DCT, half-pel interpolation, pixel averaging, and pixel addition. The VLIW Core's two-cluster architecture with 128-bit data path per cluster and partitioned operations achieves a high throughput on 8-bit and 16-bit pixel operations. Also, to avoid the VLIW Core from waiting for data, a dedicated data transfer engine called Data Streamer moves data between MAP1000A, external memory, and I/O devices in parallel with the VLTCY Core's execution. The MPEG-2 video decoder on MAP1000A is written entirely in the C language, which is a significant advantage over previous processors which required assembly-language programming At 220 MHz clock frequency, the MPEG-2 decoder takes less than 40% of the MAP1000A's cycles. Two MP@ML streams can be decoded simultaneously in real time, with enough cycles remaining to perform other tasks such as the audio and system decoding.