Improving the effectiveness of floating point arithmetic

被引:6
|
作者
Fahmy, HAH [1 ]
Liddicoat, AA [1 ]
Flynn, MJ [1 ]
机构
[1] Stanford Univ, Comp Syst Lab, Stanford, CA 94305 USA
关键词
D O I
10.1109/ACSSC.2001.987049
中图分类号
TP31 [计算机软件];
学科分类号
081202 ; 0835 ;
摘要
This work presents several techniques to improve the effectiveness of floating point arithmetic computations. A partially redundant number system is proposed as an internal format for arithmetic operations. The redundant number system enables carry free arithmetic operations to improve performance. Conversion from the proposed internal format back to the standard IEEE format is done only when an operand is written to memory. Efficient arithmetic units for floating point addition, multiplication and division are proposed using the redundant number system. This proposed system achieves overall better performance across all of the functional units when compared to state-of-the-art designs. The proposed internal format and arithmetic units comply with all the rounding modes of the IEEE 754 floating point standard.
引用
收藏
页码:875 / 879
页数:5
相关论文
共 50 条
  • [31] Design of Floating Point Units for Interval Arithmetic
    Amaricai, Alexandru
    Vladutiu, Mircea
    Boncalo, Oana
    PRIME: PROCEEDINGS OF THE CONFERENCE 2009 PHD RESEARCH IN MICROELECTRONICS AND ELECTRONICS, 2009, : 12 - 15
  • [32] Quantum Circuits for Floating-Point Arithmetic
    Haener, Thomas
    Soeken, Mathias
    Roetteler, Martin
    Svore, Krysta M.
    REVERSIBLE COMPUTATION, RC 2018, 2018, 11106 : 162 - 174
  • [33] Floating point arithmetic teaching for computational science
    Fernández, JJ
    García, I
    Garzón, EM
    FUTURE GENERATION COMPUTER SYSTEMS-THE INTERNATIONAL JOURNAL OF ESCIENCE, 2003, 19 (08): : 1321 - 1334
  • [34] MODIFIED FLOATING-POINT ARITHMETIC.
    Anon
    IBM technical disclosure bulletin, 1985, 28 (05): : 1836 - 1837
  • [35] Parameterised floating-point arithmetic on FPGAs
    Jaenicke, A
    Luk, W
    2001 IEEE INTERNATIONAL CONFERENCE ON ACOUSTICS, SPEECH, AND SIGNAL PROCESSING, VOLS I-VI, PROCEEDINGS: VOL I: SPEECH PROCESSING 1; VOL II: SPEECH PROCESSING 2 IND TECHNOL TRACK DESIGN & IMPLEMENTATION OF SIGNAL PROCESSING SYSTEMS NEURALNETWORKS FOR SIGNAL PROCESSING; VOL III: IMAGE & MULTIDIMENSIONAL SIGNAL PROCESSING MULTIMEDIA SIGNAL PROCESSING, 2001, : 897 - 900
  • [36] FLOATING POINT ARITHMETIC AND DIGITAL-FILTERS
    RAO, BD
    IEEE TRANSACTIONS ON SIGNAL PROCESSING, 1992, 40 (01) : 85 - 95
  • [37] Efficient Secure Arithmetic on Floating Point Numbers
    Omori, Wakana
    Kanaoka, Akira
    ADVANCES IN NETWORK-BASED INFORMATION SYSTEMS, NBIS-2017, 2018, 7 : 924 - 934
  • [38] Arithmetic Coding for Floating-Point Numbers
    Fischer, Marc
    Riedel, Oliver
    Lechler, Armin
    Verl, Alexander
    2021 IEEE CONFERENCE ON DEPENDABLE AND SECURE COMPUTING (DSC), 2021,
  • [39] Hardware support for UNUM floating point arithmetic
    Bocco, Andrea
    Durand, Yves
    de Dinechin, Florent
    2017 13TH CONFERENCE ON PH.D. RESEARCH IN MICROELECTRONICS AND ELECTRONICS (PRIME), 2017, : 93 - 96
  • [40] Floating-point arithmetic in the Coq system
    Melquiond, Guillaume
    INFORMATION AND COMPUTATION, 2012, 216 : 14 - 23