Ripple Current Reduction Using Interleaving Technique for Three-level ZVZCS DC-DC Converter

This paper presents an output current ripple reduction technique for a three-level ZVZCS DC-DC converter which the output power is controlled by phase-shifted pulse width modulation (PSPWM). By means of 2 circuits of half bridge three-level DC-DC converter which operated by 90 degrees phase difference or interleaving technique, as the results, the ripple of output current waveform is reduced significantly. The prototype of proposed circuit was designed and tested at 470 W of rated power, 310 V of input voltage, 0-48 V of output voltage and 50 kHz of switching frequency in order to compare the experimental results between interleaving and non-interleaving technique. It is found that the interleaving technique can reduce the ripple current on output current waveform for all phase-shifted angles. Finally, all switches in circuit can achieve soft-switching conditions and the maximum efficiency of converter is 93.7 %.