Simulation of the processor array with reconfigurable bus system on the PRAM

被引:0
|
作者
Lin, SS
机构
[1] Department of Information and Computer Education, National Taiwan Normal University, Taipei
关键词
computation model; parallel random access machine; processor array; reconfigurable bus system;
D O I
10.1080/02533839.1996.9677825
中图分类号
T [工业技术];
学科分类号
08 ;
摘要
A processor array with a reconfigurable bus system (abbreviated to PARBS) is a computation model which consists of a processor array and a reconfigurable bus system. It is a very powerful computation model in that many problems can be solved efficiently. The power of a computation model usually indicates how fast a problem can be solved under that model. In [16], Wang and Chen have shown that the two-dimensional PARBS is at least as powerful as the PRAM (parallel random access machine). That is, if a problem can be solved in O(f(n)) time on the PRAM with n processors and m memory cells, it can also be solved in O(f(n)) time on the two-dimensional PARBS with n*m processors. The reverse assertion has not been proven yet. The difficulty arises from the great flexibility in the configurations of reconfigurable system. In this paper, we show that a restricted version of the PARBS, called ORTHOGONAL PARBS, which includes all one-dimensional PARBS with two-neighbor connections and many two-dimensional PARBS with four-neighbor connections used by some researchers, can be simulated accordingly on the SUM CRCW PRAM. That is, if a problem can be solved in O(f(n)) time on the ORTHOGONAL PARBS with n processors, it can also be solved in O(f(n)) time and O(n) memory cells on the SUM CRCW PRAM.
引用
下载
收藏
页码:615 / 622
页数:8
相关论文
共 50 条
  • [31] Design of reconfigurable array processor for multimedia application
    Zhu Yun
    Lin Jiang
    Shuai Wang
    Xingjie Huang
    Hui Song
    Xueting Li
    Multimedia Tools and Applications, 2018, 77 : 3639 - 3657
  • [32] Design of reconfigurable array processor for multimedia application
    Yun, Zhu
    Jiang, Lin
    Wang, Shuai
    Huang, Xingjie
    Song, Hui
    Li, Xueting
    MULTIMEDIA TOOLS AND APPLICATIONS, 2018, 77 (03) : 3639 - 3657
  • [33] IMAGE COMPONENT LABELING ON RECONFIGURABLE PROCESSOR ARRAY
    MARESCA, M
    BAGLIETTO, P
    GIORDANO, A
    MICROPROCESSING AND MICROPROGRAMMING, 1993, 38 (1-5): : 327 - 334
  • [34] Constant-time algorithms for minimum spanning tree and related problems on processor array with reconfigurable bus systems
    Pan, Tien-Tai
    Lin, Shun-Shii
    1600, Oxford University Press (45):
  • [35] Constant-time algorithms for minimum spanning tree and related problems on processor array with reconfigurable bus systems
    Pan, TT
    Lin, SS
    COMPUTER JOURNAL, 2002, 45 (02): : 174 - 186
  • [36] Fast nearest neighbor algorithms on a linear array with a reconfigurable pipelined bus system
    Pan, Y
    Li, KQ
    Zheng, SQ
    THIRD INTERNATIONAL SYMPOSIUM ON PARALLEL ARCHITECTURES, ALGORITHMS, AND NETWORKS, PROCEEDINGS (I-SPAN '97), 1997, : 444 - 450
  • [37] Multiple Addition and Prefix Sum on a Linear Array with a Reconfigurable Pipelined Bus System
    Amitava Datta
    The Journal of Supercomputing, 2004, 29 : 303 - 317
  • [38] Multiple addition and prefix sum on a linear array with a reconfigurable pipelined bus system
    Datta, A
    JOURNAL OF SUPERCOMPUTING, 2004, 29 (03): : 303 - 317
  • [39] One Dimensional SIMD Array Processor with Segmentable Bus
    Zhang, Fa-cun
    Liu, Wei
    Wang, Qian-kun
    CEIS 2011, 2011, 15
  • [40] The flexible processor - Dynamically reconfigurable logic array for personal-use emulation system
    Ohkawa, T
    Nozawa, T
    Fujibayashi, M
    Miyamoto, N
    Leo, K
    Kita, S
    Kotani, K
    Ohmi, T
    2003 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS, 2003, : 279 - 282