A Dynamically Reconfigurable Multi-ASIP Architecture for Multistandard and Multimode Turbo Decoding

被引：2

作者：

Lapotre, Vianney ^{[1
]}

Murugappa, Purushotham ^{[2
]}

Gogniat, Guy ^{[1
]}

Baghdadi, Amer ^{[2
]}

Huebner, Michael ^{[3
]}

Diguet, Jean-Philippe ^{[1
]}

机构：

[1] Univ Bretagne Sud, Lab Sci & Informat Technol Commun & Knowledge, F-56100 Lorient, France

[2] Telecom Bretagne, Lab Sci & Informat Technol Commun & Knowledge, F-9200 Plouzane, France

[3] Ruhr Univ Bochum, D-44801 Bochum, Germany

来源：

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS | 2016年 / 24卷 / 01期

关键词：

Application specific instruction-set processor (ASIP); dynamic configuration; turbo codes (TCs); wireless communication; DESIGN;

D O I：

10.1109/TVLSI.2015.2396941

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

The multiplication of wireless communication standards is introducing the need of flexible and reconfigurable multistandard baseband receivers. In this context, multiprocessor turbo decoders have been recently developed in order to support the increasing flexibility and throughput requirements of emerging applications. However, these solutions do not sufficiently address reconfiguration performance issues, which can be a limiting factor in the future. This brief presents the design of a reconfigurable multiprocessor architecture for turbo decoding achieving very fast reconfiguration without compromising the decoding performances.

引用

页码：383 / 387

页数：5

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