Testability analysis for crosstalk faults in VLSI circuits by using binary decision diagrams

As the increase of circuit density and switching speed, the crosstalk faults may arise in the adjacent signal lines of VLSI circuits, which are the interference effects caused by parasitic inductance and capacitance coupling. The crosstalk delay fault is one of the crosstalk faults, it may create the additional delay in the circuit, thus it may result in the unexpected time sequence and logic function errors. In this paper, a new approach is presented for the testability analysis of crosstalk delay faults, the approach can decide whether there are test vectors for a crosstalk delay fault in a circuit. First of all, several binary decision diagrams of a circuit are constructed. Secondly, the testability analysis of crosstalk delay faults is carried out by performing a lot of operations on these binary decision diagrams. One advantage of the approach in this paper is that the test vectors of crosstalk faults can be generated quickly after the testability analysis has been carried out, therefore the approach is able to cut down the test time in comparison with generating the test vectors directly.