Three-Phase Grid Synchronization PLL using Multiple Delayed Signal Cancellation under Adverse Grid Voltage Conditions

Grid synchronization of distributed generation (DG) plays an important role for effective power transfer from DG units to the utility grid. Usually, the synchronous reference frame based phase-locked loop (PLL) is a common technique. However, there is a compromise between steady-state accuracy and dynamic performance of PLL especially when the grid voltages contain harmonics and /or unbalances. In order to improve the dynamic performance of PLL under adverse grid voltage conditions, different types of in-loop and pre-filters are proposed recently. This paper presents a novel filtering technique for extracting fundamental frequency positive sequence (FFPS) component of the grid voltage based on multiple delayed signal cancellation (MDSC). The MDSC filter has more flexibility to configure the lowest undesired harmonics and hence it can have fast response time. Moreover, to reduce the computational burden, a simplified structure is derived in this paper. The MDSC operator is used as a pre-filter to improve dynamic performances of the PLL. Both simulation studies and experimental results are presented to demonstrate the effectiveness of the proposed PLL method.