Grid Synchronization PLL Based on Cascaded Delayed Signal Cancellation

During the grid synchronization of distributed generation (DG) units, phase-locked loop (PLL) is well accepted as an efficient approach to detect grid phase angle. Conventional PLL schemes used in DG controller have to compromise between steady-state accuracy and transient dynamics when grid voltage is polluted by unbalance and harmonics. To simultaneously realize good steady-state and transient performances, this paper proposes a general delayed signal cancellation (DSC) operator, which can be tailored to eliminate any specified harmonic. The proposed DSC operator can be further cascaded to stepwise reject all undesired harmonics. Then the conditioned voltage signal can be used in PLL loop to achieve fast transient response state error caused by harmonics. Based on differently configured DSC operators, two PLL designs are then developed, namely CDSC-PLL1 and CDSC-PLL2. Specifically, CDSC-PLL1 is aimed for grid voltage with unbalance and odd/even harmonics, while CDSC-PLL2 further addresses asymmetrical harmonics, i.e., harmonics arising from asymmetrically distorted three-phase voltages. By introducing a frequency feedback loop, the proposed PLL can operate properly during considerable frequency variations, even when a phase jump or severe harmonics are also present. All proposed PLL designs have very simple structure and can be easily implemented. The superior performance is confirmed by experimental results.