FPGA-Based Hardware Acceleration for Boolean Satisfiability

被引：16
|
作者：
Gulati, Kanupriya [1 ]
Paul, Suganth
Khatri, Sunil P. [1 ]
Patil, Srinivas
Jas, Abhijit
机构：
[1] Texas A&M Univ, College Stn, TX 77843 USA
来源：
ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS | 2009年 / 14卷 / 02期
关键词：
Performance; Algorithms; Design; Boolean satisfiabilty (SAT); boolean constant propagation (BCP); conflict induced clauses; non-chronological backtrack; FPGA;
D O I：
10.1145/1497561.1497576
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
We present an FPGA-based hardware solution to the Boolean satisfiability (SAT) problem, with the main goals of scalability and speedup. In our approach the traversal of the implication graph as well as conflict clause generation are performed in hardware, in parallel. The experimental results and their analysis, along with the performance models are discussed. We show that an order of magnitude improvement in runtime can be obtained over MiniSAT (the best-in-class software based approach) by using a Virtex-4 (XC4VFX140) FPGA device. The resulting system can handle instances with as many as 10K variables and 280K clauses.
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页数：11
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